In non-punch-through (NPT) insulated gate bipolar transistors (IGBTs) such as are described for example in the document by J. Yamashita et al. (IEEE 1997, pp. 109-112), a lightly doped drift layer of a first charge carrier type directly adjoins the electrode of a second charge carrier type. These IGBTs are distinguished by the fact that the drift layer, for taking up a high blocking voltage, has a larger thickness and higher doping in comparison with the punch-through (PT) IGBTs described below. Owing to the larger thickness of the drift layer, higher losses are generated in the IGBT. In the case of a fault, a short-circuit current with short current spike can occur during the turn-on of the IGBT, or short-circuit current pulses can occur during operation in the turned-on state of the IGBT. On account of such a short-circuit current, the IGBT can lose its gate control and the current can continue to rise through to the destruction of the IGBT. In the case of NPT IGBTs it is advantageous that the electrode injection efficiency can be kept low without adversely influencing the robustness of the IGBT under short-circuit conditions.
In the case of punch-through (PT) IGBTs a highly doped stop layer of the first charge carrier type is introduced between the drift layer and the electrode, whereby it becomes possible to use thinner drift layers at the same blocking voltages in comparison with NPT IGBTs. The resistance is thereby reduced and lower losses occur in the turned-on IGBT as well as during the switching of the IGBT. However, the robustness of the PT IGBTs under short-circuit conditions is poorer than in the case of the NPT IGBTs.
In order to combine the advantages of PT IGBTs with those of NPT IGBTs, soft-punch-through (SPT) IGBTs have been developed, the stop layer of which, although more highly doped than the drift layer, is more lightly doped than the stop layer of a PT IGBT. The stop layer is produced by particles of the first charge carrier type being indiffused deep into a layer of the same charge carrier type. Stop layers produced in this way have a thickness of 5-60 μm. In order to drive the particles deep into the layer, long diffusion times are required. As a result, defects which can considerably reduce the blocking voltage are produced in the layer.
The document EP 1 237 200 describes a method for producing power semiconductors for operation at low blocking voltages up to 600 V. A 25 to 60 μm thin (n−)-doped drift layer is grown epitaxially on an n-doped, 625 μm thick first stop layer. The emitter is then produced and the n-doped layer is subsequently trimmed to a remaining part, such that the total thickness of the wafer from the emitter to the n-doped layer is 60 to 80 μm. A second, (n+) doped stop layer is produced by diffusion in the n-doped layer at the side at which the layer was trimmed, and an anode is formed at this side. In order to produce the second stop layer, the wafer is exposed to high temperatures as a result of the diffusion method, which is problematic for the emitter produced beforehand. Through the introduction of the second stop layer, the anode injection and the punch-through are controlled in semiconductors having low blocking voltages. This method is only suitable for producing power semiconductors for operation at low blocking voltages because the drift layer is thin in semiconductors of this type, and so the method for producing the drift layer by means of epitaxial growth is still economically tenable.